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1. general description the 74lvc2g32 provides a 2-input or gate function. inputs can be driven from either 3.3 v or 5 v devices. this feature allows the use of these devices as translators in a mixed 3.3 v and 5 v environment. this device is fully speci?ed for partial power-down applications using i off . the i off circuitry disables the output, preventing a damaging back?ow current through the device when it is powered down. 2. features n wide supply voltage range from 1.65 v to 5.5 v n 5 v tolerant outputs in the power-down mode n high noise immunity n 24 ma output drive (v cc = 3.0 v) n cmos low power consumption n complies with jedec standard: u jesd8-7 (1.65 v to 1.95 v) u jesd8-5 (2.3 v to 2.7 v) u jesd8-b/jesd36 (2.7 v to 3.6 v) n latch-up performance exceeds 250 ma n direct interface with ttl levels n inputs accept voltages up to 5 v n esd protection: u hbm eia/jesd22-a114e exceeds 2000 v u mm eia/jesd22-a115-a exceeds 200 v n multiple package options n speci?ed from - 40 c to +85 c and - 40 c to +125 c 74lvc2g32 dual 2-input or gate rev. 06 27 february 2008 product data sheet
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 2 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate 3. ordering information 4. marking 5. functional diagram table 1. ordering information type number package temperature range name description version 74lvc2g32dp - 40 c to +125 c tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm sot505-2 74lvc2g32dc - 40 c to +125 c vssop8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm sot765-1 74lvc2g32gt - 40 c to +125 c xson8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 1.95 0.5 mm sot833-1 74lvc2g32gm - 40 c to +125 c xqfn8u plastic extremely thin quad ?at package; no leads; 8 terminals; utlp based; body 1.6 1.6 0.5 mm sot902-1 table 2. marking codes type number marking code 74lvc2g32dp v32 74lvc2g32dc v32 74lvc2g32gt v32 74lvc2g32gm v32 fig 1. logic symbol fig 2. iec logic symbol 001aah791 1a 1b 1y 2a 2b 2y 001aah792 3 1 3 1 fig 3. logic diagram (one gate) mna166 b a y
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 3 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate 6. pinning information 6.1 pinning 6.2 pin description fig 4. pin con?guration tssop8 and vssop8 74lvc2g32 1a v cc 1b 1y 2y 2b gnd 2a 001aab742 1 2 3 4 6 5 8 7 fig 5. pin con?guration xson8 fig 6. pin con?guration xqfn8u 74lvc2g32 2b 1y v cc 2a 2y 1b 1a gnd 001aab743 36 27 18 45 transparent top view 001aae994 1b 2b 1a v cc 2y 1y gnd 2a transparent top view 3 6 4 1 5 8 7 2 terminal 1 index area 74lvc2g32 table 3. pin description symbol pin description tssop8, vssop8 xson8 xqfn8u 1a 1 1 7 data input 1b 2 2 6 data input 2y 3 3 5 data output gnd444g round (0 v) 2a 5 5 3 data input 2b 6 6 2 data input 1y 7 7 1 data output v cc 8 8 8 supply voltage
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 4 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate 7. functional description [1] h = high voltage level; l = low voltage level. 8. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] when v cc = 0 v (power-down mode), the output voltage can be 5.5 v in normal condition. [3] for tssop8 package: above 55 c the value of p tot derates linearly with 2.5 mw/k. for vssop8 package: above 110 c the value of p tot derates linearly with 8 mw/k. for xson8 and xqfn8u packages: above 45 c the value of p tot derates linearly with 2.4 mw/k. table 4. function table [1] input output na nb ny lll lhh hl h hhh table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +6.5 v v i input voltage [1] - 0.5 +6.5 v v o output voltage active mode [1] - 0.5 v cc + 0.5 v power-down mode [2] - 0.5 +6.5 v i ik input clamping current v i <0v - 50 - ma i ok output clamping current v o < 0 v or v o >v cc - 50 ma i o output current v o =0vtov cc - 50 ma i cc supply current - 100 ma i gnd ground current - 100 - ma t stg storage temperature - 65 +150 c p tot total power dissipation t amb = - 40 c to +125 c [3] - 300 mw
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 5 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate 9. recommended operating conditions 10. static characteristics table 6. operating conditions symbol parameter conditions min max unit v cc supply voltage 1.65 5.5 v v i input voltage 0 5.5 v v o output voltage active mode 0 v cc v power-down mode 0 5.5 v t amb ambient temperature - 40 +125 c d t/ d v input transition rise and fall rate v cc = 1.65 v to 2.7 v - 20 ns/v v cc = 2.7 v to 5.5 v - 10 ns/v table 7. static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = - 40 c to +85 c [1] v ih high-level input voltage v cc = 1.65 v to 1.95 v 0.65 v cc -- v v cc = 2.3 v to 2.7 v 1.7 - - v v cc = 2.7 v to 3.6 v 2.0 - - v v cc = 4.5 v to 5.5 v 0.7 v cc -- v v il low-level input voltage v cc = 1.65 v to 1.95 v - - 0.35 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 2.7 v to 3.6 v - - 0.8 v v cc = 4.5 v to 5.5 v - - 0.3 v cc v v oh high-level output voltage v i =v ih or v il i o = - 100 m a; v cc = 1.65 v to 5.5 v v cc - 0.1 - - v i o = - 4 ma; v cc = 1.65 v 1.2 1.53 - v i o = - 8 ma; v cc = 2.3 v 1.9 2.13 - v i o = - 12 ma; v cc = 2.7 v 2.2 2.50 - v i o = - 24 ma; v cc = 3.0 v 2.3 2.60 - v i o = - 32 ma; v cc = 4.5 v 3.8 4.10 - v v ol low-level output voltage v i = v ih or v il i o = 100 m a; v cc = 1.65 v to 5.5 v - - 0.1 v i o = 4 ma; v cc = 1.65 v - 0.08 0.45 v i o = 8 ma; v cc = 2.3 v - 0.14 0.3 v i o = 12 ma; v cc = 2.7 v - 0.19 0.4 v i o = 24 ma; v cc = 3.0 v - 0.37 0.55 v i o = 32 ma; v cc = 4.5 v - 0.43 0.55 v i i input leakage current v i = 5.5 v or gnd; v cc = 0 v to 5.5 v - 0.1 5 m a i off power-off leakage current v i or v o = 5.5 v; v cc = 0 v - 0.1 10 m a
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 6 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate [1] all typical values are measured at t amb = 25 c. i cc supply current v i = 5.5 v or gnd; v cc = 1.65 v to 5.5 v; i o =0a - 0.1 10 m a d i cc additional supply current per pin; v i = v cc - 0.6 v; i o = 0 a; v cc = 2.3 v to 5.5 v - 5 500 m a c i input capacitance - 2.5 - pf t amb = - 40 c to +125 c v ih high-level input voltage v cc = 1.65 v to 1.95 v 0.65 v cc -- v v cc = 2.3 v to 2.7 v 1.7 - - v v cc = 2.7 v to 3.6 v 2.0 - - v v cc = 4.5 v to 5.5 v 0.7 v cc -- v v il low-level input voltage v cc = 1.65 v to 1.95 v - - 0.35 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 2.7 v to 3.6 v - - 0.8 v v cc = 4.5 v to 5.5 v - - 0.3 v cc v v oh high-level output voltage v i =v ih or v il i o = - 100 m a; v cc = 1.65 v to 5.5 v v cc - 0.1 - - v i o = - 4 ma; v cc = 1.65 v 0.95 - - v i o = - 8 ma; v cc = 2.3 v 1.7 - - v i o = - 12 ma; v cc = 2.7 v 1.9 - - v i o = - 24 ma; v cc = 3.0 v 2.0 - - v i o = - 32 ma; v cc = 4.5 v 3.4 - - v v ol low-level output voltage v i = v ih or v il i o = 100 m a; v cc = 1.65 v to 5.5 v - - 0.1 v i o = 4 ma; v cc = 1.65 v - - 0.70 v i o = 8 ma; v cc = 2.3 v - - 0.45 v i o = 12 ma; v cc = 2.7 v - - 0.60 v i o = 24 ma; v cc = 3.0 v - - 0.80 v i o = 32 ma; v cc = 4.5 v - - 0.80 v i i input leakage current v i = 5.5 v or gnd; v cc = 0 v to 5.5 v - - 20 m a i off power-off leakage current v i or v o = 5.5 v; v cc = 0 v - - 20 m a i cc supply current v i = 5.5 v or gnd; v cc = 1.65 v to 5.5 v; i o =0a --40 m a d i cc additional supply current per pin; v i = v cc - 0.6 v; i o = 0 a; v cc = 2.3 v to 5.5 v - - 5000 m a table 7. static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 7 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate 11. dynamic characteristics [1] typical values are measured at nominal v cc and at t amb =25 c. [2] t pd is the same as t plh and t phl . [3] c pd is used to determine the dynamic power dissipation (p d in m w). p d = c pd v cc 2 f i n + s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; s (c l v cc 2 f o ) = sum of outputs. 12. waveforms table 8. dynamic characteristics voltages are referenced to gnd (ground 0 v); for test circuit see figure 8 . symbol parameter conditions - 40 c to +85 c - 40 c to +125 c unit min typ [1] max min max t pd propagation delay na, nb to ny; see figure 7 [2] v cc = 1.65 v to 1.95 v 1.3 3.9 8.8 1.3 11 ns v cc = 2.3 v to 2.7 v 0.8 2.4 4.7 0.8 5.9 ns v cc = 2.7 v 0.8 2.7 4.8 0.8 6.0 ns v cc = 3.0 v to 3.6 v 0.9 2.2 4.2 0.9 5.3 ns v cc = 4.5 v to 5.5 v 0.7 1.7 3.2 0.7 4.0 ns c pd power dissipation capacitance per gate; v i = gnd to v cc [3] -14-- -pf measurement points are given in t ab le 9 . v ol and v oh are typical output voltage levels that occur with the output load. fig 7. input (na, nb) to output (ny) propagation delays mna224 na, nb input ny output t plh t phl gnd v i v m v m v oh v ol
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 8 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate table 9. measurement points supply voltage input output v cc v m v m 1.65 v to 1.95 v 0.5v cc 0.5v cc 2.3 v to 2.7 v 0.5v cc 0.5v cc 2.7 v 1.5 v 1.5 v 3.0 v to 3.6 v 1.5 v 1.5 v 4.5 v to 5.5 v 0.5v cc 0.5v cc test data is given in t ab le 10 . de?nitions for test circuit: r l = load resistor c l = load capacitance including jig and probe capacitance r t = termination resistance should be equal to output impedance z o of the pulse generator v ext = test voltage for switching times fig 8. load circuitry for switching times v ext v cc v i v o 001aae235 dut c l r t r l r l pulse generator v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f table 10. test data supply voltage input load v ext v cc v i t r , t f c l r l t plh , t phl 1.65 v to 1.95 v v cc 2.0 ns 30 pf 1 k w open 2.3 v to 2.7 v v cc 2.0 ns 30 pf 500 w open 2.7 v 2.7 v 2.5 ns 50 pf 500 w open 3.0 v to 3.6 v 2.7 v 2.5 ns 50 pf 500 w open 4.5 v to 5.5 v v cc 2.5 ns 50 pf 500 w open
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 9 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate 13. package outline fig 9. package outline sot505-2 (tssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (1) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.00 0.95 0.75 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.70 0.35 8 0 0.13 0.1 0.2 0.5 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 0.47 0.33 sot505-2 - - - 02-01-16 w m b p d z e 0.25 14 8 5 q a 2 a 1 l p (a 3 ) detail x a l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm sot505-2 1.1 pin 1 index
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 10 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate fig 10. package outline sot765-1 (vssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.00 0.85 0.60 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.1 8 0 0.13 0.1 0.2 0.4 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.40 0.15 q 0.21 0.19 sot765-1 mo-187 02-06-07 w m b p d z e 0.12 14 8 5 q a 2 a 1 q l p (a 3 ) detail x a l h e e c v m a x a y 2.5 5 mm 0 scale vssop8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm sot765-1 1 pin 1 index
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 11 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate fig 11. package outline sot833-1 (xson8) terminal 1 index area references outline version european projection issue date iec jedec jeita sot833-1 - - - mo-252 - - - sot833-1 07-11-14 07-12-07 dimensions (mm are the original dimensions) xson8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 e 1 0 1 2 mm scale notes 1. including plating thickness. 2. can be visible in some manufacturing processes. unit mm 0.25 0.17 2.0 1.9 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.5 0.6 a (1) max 0.5 0.04 1 8 2 7 3 6 4 5 8 (2) 4 (2) a
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 12 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate fig 12. package outline sot902-1 (xqfn8u) references outline version european projection issue date iec jedec jeita sot902-1 mo-255 - - - - - - sot902-1 05-11-25 07-11-14 unit a max mm 0.5 a 1 0.25 0.15 0.05 0.00 1.65 1.55 0.35 0.25 0.15 0.05 dimensions (mm are the original dimensions) xqfn8u: plastic extremely thin quad flat package; no leads; 8 terminals; utlp based; body 1.6 x 1.6 x 0.5 mm b dl e 1 1.65 1.55 e e l 1 v 0.1 0.55 0.5 w 0.05 y 0.05 0.05 y 1 0 1 2 mm scale x c y c y 1 terminal 1 index area terminal 1 index area b a d e detail x a a 1 b 8 7 6 5 e 1 e 1 e e a c b ? v m c ? w m 4 1 2 3 l l 1 metal area not for soldering
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 13 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate 14. abbreviations 15. revision history table 11. abbreviations acronym description cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 12. revision history document id release date data sheet status change notice supersedes 74lvc2g32_6 20080227 product data sheet - 74lvc2g32_5 modi?cations: ? figure 1 and figure 2 : pin numbers removed from logic symbols ? figure 12 : package outline drawing updated to latest version 74lvc2g32_5 20070904 product data sheet - 74lvc2g32_4 74lvc2g32_4 20060515 product data sheet - 74lvc2g32_3 74lvc2g32_3 20050201 product speci?cation - 74lvc2g32_2 74lvc2g32_2 20040922 product speci?cation - 74lvc2g32_1 74lvc2g32_1 20031027 product speci?cation - -
74lvc2g32_6 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 06 27 february 2008 14 of 15 nxp semiconductors 74lvc2g32 dual 2-input or gate 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors 74lvc2g32 dual 2-input or gate ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 27 february 2008 document identifier: 74lvc2g32_6 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 recommended operating conditions. . . . . . . . 5 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 14 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 17 contact information. . . . . . . . . . . . . . . . . . . . . 14 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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